Designing, simulation and layout of 6bit full adder in cadence software Journal title: International Research Journal of Applied and Basic Sciences Authors: Sepideh Fazel| Tabriz Islamic Azad University, email: fazel.sepideh@gmail.com Subject(s): Public Health and Community Medicine
Reversible Multiplier with Peres Gate and Full Adder Journal title: International Journal of Electronics Communication and Computer Technology Authors: Prof. Amol D. Morankar| Dept. of Electronics and Telecommunication Engg. V.N.I.T Nagpur, India, Prof... Subject(s): Computer and Information Science, Engineering
Analysis of Self Checking Additional Adder Circuit in Combinational Circuits Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Abirami S B, Manoj K, Maruthu Pandian C, Rajesh K Subject(s): Engineering, Applied Linguistics
Comparison of Power and Delay in Different Types of Full Adder Circuit Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: N. Sabari Manoj, K. Suriya Subject(s): Engineering, Applied Linguistics
Implementation of High Speed Full Adder Using DTMOS Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Shubham Bansal, Dr. Neelam R Prakash Subject(s): Engineering, Applied Linguistics
Implementation of Full Adder using Cmos Logic Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Ravika Gupta Subject(s): Engineering, Applied Linguistics
Design of Energy Efficient Logic Using Adiabatic Technique Journal title: International Journal of Research in Computer and Communication Technology Authors: Venkanna Babu Kesavarapu, B. I . Neelgar Subject(s): Computer and Information Science, Telecommunications
A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: Mrudula Singamsetti , Sarada Musala Subject(s):
LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC Journal title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) Authors: Mr. B. Dilli kumar , , Mr. K. Charan kumar , M. Bharathi, Subject(s):
Comparative Analysis of Different Types of Full Adder Circuits Journal title: IOSR Journals (IOSR Journal of Computer Engineering) Authors: M.B Damle Subject(s):
Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: Sushil B. Bhaisare1 , Sonalee P. Suryawanshi2 , Sagar P. Soitkar Subject(s):
LOW POWER NOVEL HYBRID ADDERS FOR DATAPATH CIRCUITS IN DSP PROCESSOR Journal title: Indian Journal of Computer Science and Engineering Authors: B. Sathiyabama , Dr. S. Malarkkan Subject(s):
AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN Journal title: International Journal on Computer Science and Engineering Authors: Praveer Saxena , Prof. Dinesh Chandra , Sampath Kumar V Subject(s):
Low Power Full Adder With Reduced Transistor Count Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: M.Geetha Priya Subject(s):
Design of Low Power and Area Efficient Full Adder for ALU Using 90nm Process for Industrial Based CAD/CAM Manufacturing Units Journal title: International Journal of Mechanical and Production Engineering Research and Development (IJMPERD ) Authors: Hariharan K, Raajan N.R, Manikandan. R, Sekar K.R Subject(s):
